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[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] ram

Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: | Size: 1024 | Author: sri | Hits:

[Embeded-SCM Develop] fifo_core

Description: 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
Platform: | Size: 10240 | Author: 刘太联 | Hits:

[SCM] Flash_ROM_lab

Description: 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct.
Platform: | Size: 3072 | Author: 劳杰勇 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] gencontrol

Description: 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
Platform: | Size: 1024 | Author: ted yang | Hits:

[OS Develop] fifodd

Description: 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
Platform: | Size: 79872 | Author: tangyi | Hits:

[VHDL-FPGA-Verilog] FPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: VHDL code for first in first out register
Platform: | Size: 1024 | Author: Davood | Hits:

[OS Develop] FIFOexperience

Description: 华为内部关于FIFO的经验之谈，深入了解FIFO-Huawei on the FIFO' s internal experiences
Platform: | Size: 516096 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] fifo1k_32

Description: PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Platform: | Size: 2048 | Author: dalchan | Hits:

[VHDL-FPGA-Verilog] fifi

Description: FIFO code written in VHDL
Platform: | Size: 11264 | Author: Harini | Hits:

[VHDL-FPGA-Verilog] fifo_sync

Description: 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
Platform: | Size: 1024 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] THS1206

Description: FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
Platform: | Size: 1024 | Author: LX | Hits:

[VHDL-FPGA-Verilog] fifo

Description: first in first out VHDL code
Platform: | Size: 1024 | Author: LXG | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

[Other] FIFORAM

Description: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Platform: | Size: 331776 | Author: SMILE | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
Platform: | Size: 456704 | Author: Robert Shen | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:
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